1. Field of the Invention
This invention relates to a picture-in-picture (PIP) type video signal processing circuit and a method of using the same for a multi-picture display circuit in which vertical and horizontal frequencies of a sub-picture video signal are automatically synchronized with a main-picture video signal.
2. Description of the Prior Art
Generally, a PIP type video processing circuit has been provided in a TV and a sub-channel picture, converted to a predetermined size by the PIP type video processing circuit, is superimposed on, or displayed within a main-channel picture in a display screen region of the TV. Accordingly, a user can display two pictures simultaneously, the main-channel picture and the sub-channel picture, on a display screen. Further, the TV having the PIP type video signal processing circuit and video cassette recorder (VCR) have been also combined so that a program is on a desired channel may be recorded by the VCR while such program also being displayed on the picture screen region of the TV, or so that a program on one channel can be recorded by the VCR while a program on different channel is displayed on the picture screen region.
Meanwhile, a TV combined with a PC having the PIP type video processing circuit has been disclosed in the field. Accordingly, both the RGB (red, green, blue) video signal provided from the TV and the VGA (video graphics array) video signal provided from the PC are selectively displayed on the main-picture and sub-picture regions of the display screen, respectively, in the TV combined with the PC so that the user can operate the PC while watching the TV.
FIG. 1 is a block diagram of a conventional PIP type video processing circuit utilizing a luminance/color difference signal switching method.
Referring to FIG. 1, the conventional PIP type video processing circuit includes a color decoder 1 for decoding luminance signal Y and chrominance signal C separated from a sub-picture video signal into a predetermined color model (YUV), an analog/digital (A/D) converter 2 for converting luminance Y/color difference signals provided from the color decoder 1 into the digital signal, a sampling clock generator 7 for generating the sampling clock signal (4 fcs) by receiving the chrominance signal C and supplying them to the A/D converter 2, a video compressor 3 for compressing the sub-picture video signal provided from the A/D converter 2, a single-port memory 4 for storing the sub-picture video signal compressed by the video compressor 3, a synchronizing separator 5 for separating the horizontal and vertical synchronizing signals Hsync and Vsync from the luminance signal Y, a memory controller 6 for controlling reading and writing operations of the single-port memory 4 by the horizontal and vertical synchronizing signals Hsync and Vsync separated from the luminance signal Y, an outline signal generator 9 for generating a sub-picture outline signal by the horizontal and vertical synchronizing signals Hsync and Vsync provided from the memory controller 6, a video signal output section 8 for mixing the sub-picture video signal provided from the single-port memory 4 with the outline signal provided from the outline signal generator 9, a digital/analog (D/A) converter 10 for converting the digital video signal provided from the video signal output means 8 into an analog video signal, a video mixer 11 for mixing the sub-picture video signal (YsUsVs) outputted from the D/A converter 10 with a main-picture video signal (YmUmVm) processed through a dependent main video signal processing circuit, and a RGB decoder 12 for decoding the sub-picture video signal (YUV) into the video signal (RGB).
The operation of the conventional PIP type video signal processing circuit will now be explained with reference to FIG. 2 to FIG. 6.
If a user selects the main-picture and sub-picture from the two video signals which are provided from the TV and PC, respectively, by using a controller such as a key input device, a PIP type video signal processing circuit for the main-picture region which is combined with the TV processes the main-picture video signal and the PIP type video signal processing circuit for the sub-picture video signal processes the sub-picture video signal respectively.
In the PIP type video signal processing circuit, the luminance Y and chrominance signals C are separated from the sub-picture video signal. The luminance signal and the chrominance signal, as the sub-picture video signal, are decoded into a luminance signal and a color difference signal as a new color model (U.V) by the color decoder 1, and subsequently converted into the digital video signal by the A/D converter 2. At this stage, the sampling clock generator 7 generates the sampling clock signal (4 fsc) by receiving the chrominance signal C and provides the same to the A/D converter so that the signal is to be used as the sampling clock signal in A/D converting process.
Next, the digital video signal is compressed with the predetermined size to display in a display screen by the video signal compressor 3.
FIG. 2 is a view explaining a compressing principle compressing an entire screen to a 1/4 screen for the sub-picture region.
Referring to FIG. 2, the video signal partially selected from an entire screen FS is written onto a 1/4 memory QM by the address signal selectively controlled by a writing horizontal counter WHC, writing vertical counter WVC which are provided in the video signal compressor 3. However, when the actual screen will be displayed, proper coefficients are added to the selected pixels and upper, bottom, left, and right pixels of the selected pixels so that video components excluded from the selected lines may be compensated thereon.
The video signal compressed by such manner is stored in the single-port memory 4. At this stage, the synchronizing separator 5 separates the horizontal and vertical synchronizing signals Hsync. and Vsync. from the luminance signal Y detected from the sub-picture video signal. The memory controller 6 selectively generates and supplies a write reset signal WRST, read reset signal RRST, write enable signal WEN, and read enable signal REN as shown in FIGS. 3A-3D so that the reading and writing operations of the memory 4 are synchronized with the horizontal and vertical synchronizing signals Hsync. and Vsync.
The video signal provided from the memory 4 is inputted to one terminal of the video signal output section 8 by the control signal of the memory controller 6, and mixed with the outline signal provided from the outline signal generator 9. Subsequently, the mixed video signal is converted into analogue video signal of luminance signal Ys/color difference signals Us, Vs by the D/A converter 10. Such video signal of the luminance signal Ys/color difference signals Us, Vs are mixed with a luminance signal Ym/color difference signals Um, Vm in the video mixer 11 by the control signal provided from the outline signal generator 9. Subsequently the mixed video signal is provided to the color picture tube (CPT) of the TV combined with the PC after being decoded back to the original RGB color signal (RGB) by the RGB decoder 12.
In FIG. 2, the 1/4 memory QM acts as a delay device to enable timing of the vertical synchronized PC video signal provided from an outside with the vertical synchronized TV video signal.
However, there are many vertical and horizontal frequencies for the TV and PC video signals. FIG. 4 shows representative frequency modes for the many frequencies.
Referring FIG. 4, in the event that the PC and TV video signal are displayed in the conventional PIP type video signal processing circuit, the luminance signal Y and chrominance signal C should be separated from the main-picture video signal, and decoded to luminance signal Y and color difference signal, and finally decoded back to the original TV color signal.
If the main-picture region is composed of the TV video signals, and the PC and TV video signals are displayed on the display screen, one horizontal line section 1H of the sub-picture video signal is reduced by half because the horizontal frequency of the PC video signal is twice that of the TV video signal. Accordingly, the half of the display screen shown in FIG. 5A is filled with noise and horizontally reduced by 1/2.
In another example, if the TV video signal is displayed on the main-picture region while the PC video signal is displayed on the sub-picture region, there is a problem as shown in FIG. 5B. In this example, the vertical frequency of the PC video signal in the VGA window mode is 60 Hz equal to the TV video signal. Further, in a VGA text mode, there are some problems as shown in FIG. 5A. Since the vertical frequency of the PC video signal is 70 Hz, the image of the sub-picture region rises to an upper side since two vertical synchronizing signals of the PC and TV video signals are not synchronized with each other.
In another example if the PC video signal is displayed on the main-picture region while the TV video signal is displayed on the sub-picture region, there is a problem as shown in FIG. 5C in contrast to FIG. 5A.
Meanwhile, it is noted that there is a difference between the VGA mode and the RGB mode in that the PC video signal is injected on the CPT by a non-interlaced method while the TV video signal is by an interlaced method. Accordingly, as shown in FIGS. 6A and 6B, the number of injection line is 449 lines for the vertical frequency 70 Hz of the PC video signal at the non-interlaced VGA text mode. When compared to 525 lines in the RGB mode, there is a significant difference. As a result, even though the sub-picture region is vertically fixed, a bottom section of the sub-picture region may be empty.
As described above, in the conventional PIP type video signal processing circuit in which the PC and TV video signals are simultaneously displayed on the display screen, the main-picture region is reduced or extended in horizontal direction. The conventional PIP type video signal processing circuit also displays an unstable sub-picture region due to the different vertical frequencies of the PC and TV video signals which are not synchronized with each other.